The preferred embodiments relate to electronic oscillators.
Electronic oscillators are well-known devices operable to produce an oscillating output signal, where in the case of a relaxation oscillator the output is nonsinusoidal, such as a triangle wave or a square wave. A typical relaxation oscillator, as further detailed below, includes a feedback loop and one or more capacitors that control the frequency of the oscillator output by, and in response to the time of, the charging and discharging of the capacitor(s). The relaxation oscillator output, therefore, changes state (e.g., from a rising transition to a falling transition) as the status of the capacitor(s) switches between charging and discharging.
Uses for electronic oscillators are also well-known for timing and synchronization and occur in numerous electronic circuits, devices, and industries. In many of these applications, various or all of the oscillator components are combined into an integrated circuit. As such, design considerations contemplate the oscillator as well as the overall integrated circuit. For example, with respect to the oscillator, key considerations are to reduce the effects of non-idealities in the oscillator and to ensure desired precision or lack of error in the output frequency. As another example, with respect to the integrated circuit, and of course the oscillator it includes, power consumption should be minimized, particularly in instances where the device for which the oscillator is operating has limited or consumable power (e.g., in battery-operated applications).
By way of further background, FIG. 1 illustrates a schematic of a typical prior art relaxation oscillator 10. Oscillator 10 includes a current stage 100, a charging stage 200, and a comparator/output stage 300.
Current/reference stage 100 includes a differential amplifier 102 having a non-inverting input connected to receive a bias voltage, VBG, and an inverting input coupled to a resistor R1 and to the drain of p-channel transistor (P1). The output of amplifier 102 is connected to the gate of p-channel transistor P1 and also to the respective gates of each of p-channel power transistors MP1 and MP2, which, along with p-channel transistor P1, all have their sources connected to a voltage supply, VDDLDO, from a low dropout voltage source. The drain of transistor MP1 is connected to a node 202 of charging stage 200, and the drain of transistor MP2 is connected to a node VREF, which is the voltage across a reference resistor Rf, relative to ground.
In general and shown schematically to the left of charging stage 200, there is an p-channel transistor P2 with its source connected to node 202, its drain connected to a node 204, and its gate connected to a first output /fCLKO of comparator/output stage 300. Node 204 is further connected to a drain of an re-channel transistor N1 that has its drain connected to ground and its gate connected to first output /fCLKO of comparator/output stage 300. Node 204 is also connected to a first input of a comparator C1 in comparator/output stage 300, and node 204 is also connected through a capacitor Cf1 to a reference voltage, which in the preferred embodiments is ground.
In general and shown schematically to the right of charging stage 200, there is a p-channel transistor P3 with its source connected to node 202, its drain connected to a node 206, and its gate connected to a second output fCLKO (complementary to first output /fCLKO) of comparator/output stage 300. Node 206 is further connected to a drain of an n-channel transistor N2 that has its source connected to ground and its gate to second output fCLKO of comparator/output stage 300. Node 206 is also connected to a first input of a comparator C2 in comparator/output stage 300, and node 206 is also connected through a capacitor Cf2 to ground.
As already suggested above, comparator/output stage 300 includes comparators C1 and C2. Each of these comparators has a first and second input, with the respective first inputs already described, and the second inputs both connected to receive the reference voltage, VREF. The respective output of each of comparators C1 and C2 is connected to a respective first input of respective NAND gates ND1 and ND2, with the second input of NAND gates ND1 and ND2 cross-coupled to the output of the opposite NAND gate, ND2 and ND1, respectively. Moreover, the output of NAND gate ND1 is connected through an inverter IN1 to provide first output /fCLKO, and the output of NAND gate ND2 is connected through an inverter IN2 to provide second output fCLKO.
The operation of oscillator 10 is as follows, and should be generally understood to provide an oscillating signal, which is complementary at first output /fCLKO and second output fCLKO. More specifically, as the feedback to amplifier 102 reaches equilibrium, power transistors MP1 and MP2 are enabled to source both node 202 and provide current through reference resistor RF, thereby establishing the reference voltage VREF to comparators C1 and C2. Given the complementary conductivity type of transistor P2 relative to transistor N1, and similarly of transistor P3 relative to transistor N2, after startup one of transistors P2 or P3 is enabled, while the other is disabled, and at the same time one of the common-gate-connected transistors N1 or N2 is therefore disabled, while the other is enabled. For example, assuming transistor P2 is enabled then transistor N1 is disabled; at the same time, transistor P3 is disabled and transistor N2 is also enabled. Such states allow capacitor Cf1 to begin to charge, while capacitor Cf2 begins to discharge and, thus, nodes 204 and 206 provide opposing voltages to the first inputs of comparator C1 and C2. These voltages are compared the second inputs which receive VREF, eventually causing the respective outputs of comparators C1 and C2 to reverse digital state, which pass through NAND gates ND1 and ND2, and inverters IN1 and IN2, likewise causing complementary outputs /fCLKO and fCLKO also to change state. These complementary outputs /fCLKO and fCLKO are fed back to the gates of transistor pairs P2/N1 and P3/N2, so that, for example, transistor P2 is disabled, transistors P3 and N1 are enabled, while transistor N2 is also disabled, which consequently causes an eventual reverse in the complementary outputs /fCLKO and fCLKO. In this manner, therefore, one of capacitors Cf1 and Cf2 charges while the other discharges, and the outputs of /fCLKO and fCLKO provide an oscillating signal, with a timing constant dependent on the values of Cf1 and Cf2 (typically matched) and reference resistor Rf.
While the above oscillator 10 and comparable approaches have proven useful and workable in various implementations, the present inventors recognize that such approaches may have drawbacks. For example, while ideally the frequency (and corresponding time constant) of the oscillator depends solely on the values of Cf1, Cf2, and Rf, in actuality there are non-idealities inherent in the design. For example, once VREF is met by the charge across one of Cf1 and Cf2, there is a corresponding delay in the one of the comparators C1 and C2 that detects that met threshold, and this delay adds to the period of outputs /fCLKO and fCLKO. As another example, if any of Cf1, Cf2, and Rf are integrated onto the same chip as the remaining oscillator components, additional error is introduced by the variability of capacitance and resistance values, as may exist from manufacturing variance and temperature dependence. Indeed, some architectures necessitate that these capacitors and resistor are on-chip, thereby introducing such additional error. The above approaches also may be limiting in the sense that certain designs that require an oscillator may demand relatively high precision, in which case the above approach may not be not usable.
Given the preceding, the present inventors have identified potential improvements to the prior art, as are further detailed below.